IRCST=0, IREFST=0, PLLST=0, CLKST=00, LOCK0=0, LOLS0=0
MCG Status Register
| IRCST | Internal Reference Clock Status 0 (0): Source of internal reference clock is the slow clock (32 kHz IRC). 1 (1): Source of internal reference clock is the fast clock (4 MHz IRC). |
| OSCINIT0 | OSC Initialization |
| CLKST | Clock Mode Status 0 (00): Encoding 0 - Output of the FLL is selected (reset default). 1 (01): Encoding 1 - Internal reference clock is selected. 2 (10): Encoding 2 - External reference clock is selected. 3 (11): Encoding 3 - Output of the PLL is selected. |
| IREFST | Internal Reference Status 0 (0): Source of FLL reference clock is the external reference clock. 1 (1): Source of FLL reference clock is the internal reference clock. |
| PLLST | PLL Select Status 0 (0): Source of PLLS clock is FLL clock. 1 (1): Source of PLLS clock is PLL output clock. |
| LOCK0 | Lock Status 0 (0): PLL is currently unlocked. 1 (1): PLL is currently locked. |
| LOLS0 | Loss of Lock Status 0 (0): PLL has not lost lock since LOLS 0 was last cleared. 1 (1): PLL has lost lock since LOLS 0 was last cleared. |